Digital data are often transferred across computer and telecommunications networks. A clock signal is required to synchronize both the transmission and reception of digital data in a communications device used to transfer the data. The clock signal is used by a transmitter to drive digital data onto a communications medium at a set frequency. The clock signal is used by a receiver to recover the transmitted data from the communications medium and drive the circuits which receive the data from the receiver.
Clock signals having high precision are desirable in order to transmit and receive without losing data. A precise transmit clock aids in the efficient and loss-free reception of the transmitted data because the data transmitted using the clock has a predictable transfer frequency with consistent data transition edge positions. Data transmitted using a transmit clock having jitter, i.e. random or systematic variation in an edge position relative to an ideal edge, or that is out-of-tolerance, i.e. the fundamental frequency of the data signal deviates from the ideal frequency, must be compensated for in the receiver and, if the receiver is unable to compensate then data can be lost. Thus, receivers require precise clocks that allow the receiver to compensate for variations in the phase and frequency of the incoming data signal or stream.
A typical device used to generate a precise clock frequency is Phase-Locked Loop (PLL). Transmitters use a PLL to synthesize a high frequency transmit clock from a lower frequency reference clock because of the difficulty in distributing the high frequency clock in the presence of noise and because of the higher power consumption of a higher speed clock. Receivers use a separate PLL to accommodate differences in the phase and frequency of the incoming data relative to a reference clock frequency. Each channel for transmission or reception therefore typically requires its own PLL along with the attendant pin-out, power and circuit area requirements. As a result, integrated circuits (ICs) which use multiple serial transmitters and receivers may become too large because of the separate PLLs required to create the local clock for each channel. Also, multiple PLLs on a single chip can interfere with one another and degrade their performance.
A conventional transmit and receive pair of the prior art is shown in FIG. 1. A transmitter 10 includes a PLL 12 which receives a reference frequency F.sub.R and generates a transmit clock TX CLOCK which drives the transmit data TX DATA through D flip-flop 14 onto the transmission medium as TRANSMIT DATA. TX CLOCK is also routed back to the circuit sending TX DATA to synchronize the transfer of TX DATA into transmitter 10.
A receiver 20 also includes a PLL 22 which receives the reference frequency F.sub.R and the received data RECEIVE DATA which has been transmitted by a device similar to transmitter 10. PLL 22 adjusts its phase responsive to RECEIVE DATA in order to recover the receive clock RECOVERED CLOCK which drives D flip-flop 24 to recover the receive data RECOVERED DATA from the RECEIVE DATA signal from the transmission medium. RECOVERED CLOCK is also routed to the circuit which receives the RECOVERED DATA signal in order to synchronize the transfer of RECOVERED DATA signal from receiver 20.
In the PLL 22 in receiver 20, while the reference frequency F.sub.R controls the fundamental frequency of PLL 22, the data transitions in the RECEIVE DATA signal adjust the phase of the RECOVERED CLOCK signal generated by the PLL 22 so that the edges of RECOVERED CLOCK signal are in synchronization with the transitions of the data in RECEIVE DATA signal.
FIG. 2 illustrates another embodiment, according to the prior art, of a serial receiver clock and data recovery circuit. A phase-locked loop circuit comprises a voltage controlled oscillator (VCO) 112 to provide a clock signal at line 114. The clock signal from the VCO is input to a divide-by-N circuit 116 to divide it down to a predetermined reference frequency. A reference frequency source F.sub.R (i.e. a reference clock signal) is input at line 120 and compared to the divide-by-N clock signal in a phase-frequency detector circuit 122. If the divided clock frequency is lower than the reference frequency F.sub.R, the detector 122 asserts the "up" signal through multiplexor 126 to cause a charge pump 130 to increase a tune voltage for controlling the VCO 112. The charge pump output at line 132, typically an analog voltage, is input to a filter 134 and the filtered tuning voltage "VTune" is input to the VCO at line 136 to increase the clock frequency F.sub.1 in an effort to match it to N times the reference frequency F.sub.R.
Conversely, if and when the detector 122 determines that the clock frequency f/N is greater than the reference frequency F.sub.R at 120, it asserts a down "DOWN" signal through MUX 126 to the charge pump 130 in order to lower the tune voltage and thereby lower the frequency output by the oscillator 112. In this manner, the VCO 112, divide-by-N 116, detector 122, charge pump 130 and filter 134 form a closed loop (i.e. a phase-locked loop) for dynamically adjusting the VCO frequency in order to hold it to N times the reference frequency F.sub.R. However, merely matching the frequency of a serial data stream is insufficient to accurately recover the data. The precise phase of the data stream must be taken into account as well. To illustrate, imagine the data stream consists of a series of alternating 1's and 0's much like a square wave. If the recovered clock is out of phase, then every recovered data bit will be wrong.
To properly recover the serial clock and data, the incoming data stream at line 138 is compared to the clock frequency 114 in a phase detector circuit 140. Phase detector circuits of various types are known in the prior art and therefore are not described here in detail. If a given transition or "edge" of the clock signal 114 is ahead of or "leads" a corresponding edge of the data stream at 138, the detector circuit 140 asserts the down "DOWN" output 142. This control signal is conveyed through muliplexer 126 to the charge pump 130 to affect a slight downward adjustment of the tune voltage at line 132 which, in turn, slightly lowers the frequency of the clock signal output by the VCO 112 to move into closer synchronization with the serial data stream. Conversely, when the clock signal 114 lags behind the data stream at 138, detector circuit 140 asserts the "UP" signal through MUX 126 to cause the charge pump to slightly increase the tune voltage applied to the VCO, and thereby slightly increase the frequency of its output. Thus, the first detector 122 can be considered a coarse adjustment of the VCO loop in order to drive the VCO to the right frequency, while the phase detector 140 adjusts the phase of the clock signal 114 so as to synchronize it to the incoming data stream. Since these two signals are synchronized, the clock signal 114 provides the recovered clock signal and the recovered clock signal is used to clock flip flop 150 to recover data from the incoming data stream.
Multiplexor 126 is arranged for controllably selecting as control inputs to the charge pump 130, one at a time of the frequency detector 122 and, alternatively, the phase detector 140, in response to the select control signal 144. Generally, while a serial data stream is being received, the clock signal 114 is at the correct frequency, i.e., the frequency of the serial data stream, and the multiplexor 126 is set to couple the output of phase detector 140 to the charge pump, in order to keep the recovered clock signal synchronized to the data stream. If and when synchronization is lost, the select input 144 to the multiplexor 126 switches so as to apply the detector 122 output to the charge pump to force the VCO to N times the reference frequency. Having done so, the multiplexor can then switch back to the phase detector 140 to again synchronize with the data. In other words, when synchronization is lost, the circuit falls back to the reference frequency, temporarily, preparatory to resynchronizing to the data.
During normal operation, the phase detector 140 compares transitions in the recovered clock signal 114 to transitions in the data signal 138 as described above. This recovery technique works adequately as long as there are sufficient transitions in the data. In other words, if the data signal goes for a long time, say 50 or 100 bit units, without any transition, the tuning signal Vtune drifts and consequently the recovered clock signal frequency and phase drifts as well. Various protocols are known for encoding serial data, prior to transmission, so as to ensure that transitions occur within some predetermined maximum number of bit units. However, these encoding schemes increase overhead, and reduce effective bandwidth, and, obviously, they impose constraints on the nature of the data.
In addition, the phase of the clock within the RECEIVE DATA signal can drift beyond the range within which the clock recovery circuit can accommodate the drift. If the clock in the device transmitting the RECEIVE DATA signal is slightly greater or lesser than the specified Reference Frequency F.sub.R .times.N, then the phase of the RECEIVE DATA signal will persistently lead or lag the RECOVERED CLOCK frequency causing the charge pump to attempt to keep moving Vtune. However, the tuning voltage Vtune has a limited range. Once the voltage level reaches a limit of the range of Vtune, it is no longer possible to adjust the output of VCO 112 in order to follow the drift in the clock within the RECEIVE DATA signal. This results in the loss of synchronization with the incoming RECEIVE DATA stream and, consequently, the loss of data.
Accordingly, a need remains for device which can continuously, i.e., without limiting adjust a phase of a recovered clock without the loss of received data.